1. Field of the Invention
The present invention relates to a dynamic random access memory and, more particularly, it relates to a dynamic random access memory having a sense amplifier of a high sensitivity CMOS (complementary MOS) system which is not susceptible to deviations of various parameters during the fabricating process and internally generated noise.
2. Prior Art
FIG. 1 shows a schematic construction of a conventional dynamic random access memory (DRAM), which is disclosed in, for example, A Sub 100ns 256K DRAM in CMOS III Technology, by Roger I. Kung et al, IEEE International Solid-State Circuits Conference, Session XVIII, FAM 18.4, February 1984, pp. 278-287. In the figure, however, only a connection for the i-th bit line pair BLi and BLi is shown.
Referring to FIG. 1, the DRAM comprises word lines WL0-WLn for selecting memory cells arranged in a row, a bit line pair BLi and BLi of folded bit line type for selecting memory cells arranged in a column, an equalizing transistor 4i which turns on in response to an equalizing signal .phi.p for connecting the bit lines BLi and BLi to be at equal potential, transfer gate transistors 6i1 and 6i2 which turn on in response to a Y decoder (not shown) output Yi for connecting the bit lines BLi and BLi to I/O lines 91 and 92, respectively, a sense amplifier 10 which is activated in response to a sense amplifier driving signal S1 for raising the bit line potential of the bit line having a higher potential in the bit line pair further to the V.sub.CC level and, a sense amplifier 11 which is activated in response to a sense amplifier driving signal S2 for lowering the bit line potential of the bit line having a lower potential in the bit line pair to the ground level V.sub.SS.
Memory cells are connected to the bit lines BLi and BLi, respectively, on every other word line. In the figure, a memory cell formed of a memory transistor 2i0 and a memory capacitor 3i0 for transmitting and receiving information to and from the bit line BLi when selected by the word line WL0 and, a memory cell formed of a memory transistor 2in and a memory capacitor 3in for transmitting and receiving information to and from the bit line BLi when selected by the word line WLn are shown.
The sense amplifier 10 comprises a p channel MOS transistor li1 having its drain connected to the bit line BLi, its source connected to the sense amplifier driving signal line 12 and its gate connected to the bit line BLi and, a p channel MOS transistor li2 having its drain connected to the bit line BLi, its source connected to the driving signal line 12 and its gate connected to the bit line BLi.
The sense amplifier 11 comprises a n channel MOS transistor 5i1 having its drain connected to the bit line BLi, its source connected to the sense amplifier driving signal line 13 and its gate connected to the bit line BLi and, an n channel MOS transistor 5i2 having its drain connected to the bit line BLi, its source connected to the driving signal line 13 and its gate connected to the bit line BLi.
The sense amplifiers 10 and 11 are generally arranged at either ends of the bit line pair BLi and BLi. This is because it is difficult to provide the p channel MOS transistor and the n channel MOS transistor together in a single layout pitch for the sense amplifier.
The sense amplifier driving signal S1 is generated by a p channel MOS transistor 71 which turns on in response to a control signal .phi.S1 for connecting the signal line 12 to the supply potential V.sub.CC.
The sense amplifier driving signal S2 is generated by an n channel MOS transistor 72 which turns on in response to a driving signal .phi.S2 for connecting the signal line 13 to the ground potential V.sub.SS.
FIG. 2 is a diagram of waveforms showing the operation timing of the DRAM shown in FIG. 1. The sense (information reading) operation of a conventional DRAM will be hereinafter described with reference to FIGS. 1 and 2, for the case of reading information "1" stored in a memory capacitor 3i0 as an example.
Responsive to the fall of the external RAS signal (Ex. RAS), DRAM enters into the activated state. In the activated state, an external address signal (Ex. Add) is latched in the chip responsive to the fall of the external RAS signal. At the same time, the control signal .phi.S1 becomes a high level while the control signal .phi.S2 becomes a low level. Accordingly, MOS transistors 71 and 72 both turn off and the sense amplifier driving signals S1 and S2 both turn into a high impedance state. Then, an equalize signal .phi.P becomes a high level to render the equalizing transistor 4i conductive and the potentials of the bit lines BLi and BLi become (1/2).multidot.V.sub.CC level, that is, precisely the mid point of the supply voltage V.sub.CC and the ground voltage V.sub.SS which are amplified in the preceding cycle. Accordingly, the potential of the sense amplifier driving signal S1 becomes (1/2).multidot.V.sub.CC +.vertline.Vth(P) .vertline. level while the potential of the sense amplifier driving signal S2 becomes (1/2).multidot.V.sub.CC -.vertline.V.sub.th (N).vertline. level. Here, V.sub.th (P) is the threshold voltage of the p channel MOSFET while V.sub.th (N) is the threshold voltage of the n channel MOSFET. After the completion of the bit line equalization, the equalizing signal .phi.P becomes a low level. Then the potential of a selected word line rises in accordance with the X address signal latched in the chip responsive to the fall of the external RAS signal. In FIG. 2, the word line WL0 is selected. When the word line WL0 is selected, the n channel MOSFET 2i0 becomes conductive and the charge stored in the capacitor 3i0 is transferred to the bit line BLi so that the potential of BLi becomes higher than (1/2).SM.V.sub.CC. Then, the control signal .phi.S1 becomes a low level and the control signal .phi.S2 becomes a high level so that MOS transistors 71 and 72 turn on. Correspondingly, the sense amplifier driving signal S1 becomes a high level and the sense amplifier driving signal S2 becomes a low level to drive the p channel and n channel sense amplifiers 10 and 11, so that the difference between the potential of the bit lines BLi and BLi is amplified. Responsive to the fall of the external CAS signal (Ex. CAS), the state of the external address signal latched in the chip becomes Y address signal, which determines the bit line pair for providing a selected information to the exterior of the chip. In the case where the selected bit line pair is BLi and BLi, the signal Yi becomes a high level and amplified memory cell data is transferred to the I/O line 90 and I/O line 91 through transfer transistors 6i1 and 6i2.
In a conventional DRAM, the precharge voltage of the sense amplifier driving signal S1 is higher than the equalizing voltage of the bit line only by the threshold voltages of the p channel MOSFETs 1i1 and 1i2 while the precharge voltage of the sense amplifier driving signal S2 is lower than the equalizing voltage of the bit line only by the threshold voltages of the n channel MOSFETs 5i1 and 5i2, as described above.
In this case, there arise problems that the activation of sense amplifiers is unnecessarily quickened due to the noise superimposed on the sense amplifier driving signals and that the deterioration of the sensitivity of sense amplifiers, which is caused by the unevenness in the characteristics of transistors forming the sense amplifiers, is likely to occur, as disclosed in IECE Japan National Conference Preceedings P. 2-205, THPM 439.
The structure of a sense amplifier making equal the potentials of a bit line and a sense amplifier driving signal line which transmits driving signal to a sense amplifier formed of only nMOS transistors in response to an equalizing signal defining the equalizing period is disclosed in M. Yoshimura et al., "A 64 Kbit MOS RAM", ISSCC 78 Digest of Technical Papers PP.148-149, THPM 122,
N. Ieda et al., "A 64k MOS RAM Design", 9th Conference on Solid-State Devices (Japan) Digest of Technical Papers, PP.57-63, August 1977 and
R. Foss et al., "Simplified Peripheral Circuits for a Marginally Testable 4K RAM", ISSCC 1975, Digest of Technical Papers PP.102-103, THAM 101, 1975.
However, these prior art references do not disclose a sense amplifier of CMOS system.